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EncartaLabs

USB 3.0

( Duration: 4 Days )

The third generation of USB increases transfer rates to 5.0Gbits/s (SuperSpeed) and is backward compatible with all earlier USB 1.1/2.0 Low-Speed, Full-Speed, and High-Speed peripherals and hubs. This USB 3.0 training course covers USB 3.0 and related specifications: OTG 3.0, xHCI, UAS and AV classes

By attending USB 3.0 workshop, delegates will learn:

  • The hardware implementation and the operation of 8b10b encoder/decoder
  • Tests required to qualify the physical layer
  • PIPE interface, which is used to interconnect the Link layer and the PHY
  • Flow control mechanism, the error recovery mechanism and packet acknowledgment
  • The dual operation of USB 2.0 and USB 3.0, especially the initialization sequence used by the device to select the operation speed
  • All requirements regarding low power management, particularly the consequences on hub design.

  • Knowledge of USB 2.0 is required

COURSE AGENDA

1

System Architecture

  • Dual-bus approach
  • Dual simplex operation, concurrent IN and OUT transactions
  • Explicitely routed packet traffic instead of USB 2.0 broadcast
  • Multi-level link power management
  • New features of data flow model
  • Robustness
2

Data Flow Model

  • USB 3.0 transaction model
  • Low power link state transitions
  • Latency tolerance messaging
  • Bus interval adjustment
  • Link-level power management
  • Super-speed packet format
  • Bulk transfers, stream ID
3

Software Organization

  • Host Controller Driver, purpose of EHCI, xHCI
  • USB driver
  • Enumeration
  • Client drivers
  • Virtual communication between client drivers and endpoint through communication pipes
  • Overview of UAS and Video Display new classes
4

USB OTG 3.0

  • Objectives of OTG specification
  • Session Request Protoco
  • OTG 2.0 Host Negotiation Protocol
  • Impact on PHY layer, voltage thresholds and timeouts
  • Impact on Link and upper layers
  • Differences between OTG 2 and OTG 3
  • Embedded Host
  • OTG 3 Role Swapping Protocol
  • Symmetry, SSPC-OTG
  • Defining who is the default Host through Port capabilities
5

Physical Layer

  • AC-coupled lines
  • Receiver detection
  • Low Frequency Periodic Signaling, utilization of LFPS
  • Spread Spectrum Clocking
  • 8b10b coding scheme
  • Elasticity buffer
  • Pre-emphasis, receiver equalization
  • Lane polarity inversion detection
  • Qualifying the physical layer, eye-diagrams
  • Mathematical processing that must be performed in the oscilloscope
  • Tests required by the USB Implementer Forum
  • Loopback BERT
6

Pipe Interface

  • Interface clocking and reset
  • 16- or 32-bit data bus width
  • Rx polarity
  • Selecting transmitter voltage levels
  • Rx status codes
  • Clock tolerance compensation
  • Transmitting and detecting LFPS
  • Low power states
7

Link Layer

  • Flow control, header buffer credit
  • Buffering for data and protocol layer informations
  • Transmitter timers
  • Packetization
  • Specified encoded control sequences
  • Packet replay in case of error detection
  • Power-on reset, in-band reset
  • Link training and status state machine, understanding the main important transitions
  • Clarifying which transitions are required to enter test modes (loopback and compliance)
8

Protocol Layer

  • End-to-end communication rules
  • Burst of back-to-back data packets
  • End-to-end flow control, NRDY / ERDY transaction packets
  • Link management packet
  • TP sequences, highlighting differences with USB 2.0
  • Host flexibility in performing isochronous transactions
9

Hub

  • Repeater / forwarder
  • Routing outbound packets to explicit downstream ports
  • Aggregating inbound packets to the upstream port
  • Propagating time-stamp packet
  • USB 3.0 new descriptors and requests
10

Super Speed Power Management

  • Power states of links, devices and functions
  • Driving the power management policy
  • Related in-band protocol mechanisms
  • Inactivity timers
  • Enabling remote wake sources
11

Enumeration

  • Device states
  • Function suspend
  • New commands: SetSel()
  • Binary Device Object Store (BOS)
  • SuperSpeed device capability
  • Interface association
  • SuperSpeed endpoint companion descriptor
12

Extensible Host Controller Interface (xHci)

  • Host Controller hardware requirements
  • Memory structures, buffer rings and TRBs
  • Transfer ring, command ring, event ring
  • Transaction scheduling
  • Error detection and handling
  • Device attachment / removal
  • Utilization of doorbell
  • Single Root I/O virtualization
  • Debug capability
13

UAS Class

  • Mass storage class specification
  • SCSI architecture model
  • Command queuing
  • SAM-4 command identifier
  • Transport protocol, command Information Unit
  • Utilization of USB 3 streams
  • Task management
  • Transport protocol services
  • Pipe usage class descriptor
14

Audio / Video Class

  • AV profile definition, Basic Device Profile
  • AVCore, AVCluster, Hierarchy
  • AVFunction, AVData
  • Multi-channel audio
  • Track selector
  • Channel configuration
  • TV set example
  • Feature unit VideoControls
  • Video Processing Unit
  • AVControl interface
  • AV synchronization types, asynchronous, synchronous, adaptive
  • AV description document
  • Request and control sequences, HDMI controls
  • Support of HDCP 2

Encarta Labs Advantage

  • One Stop Corporate Training Solution Providers for over 6,000 various courses on a variety of subjects
  • All courses are delivered by Industry Veterans
  • Get jumpstarted from newbie to production ready in a matter of few days
  • Trained more than 50,000 Corporate executives across the Globe
  • All our trainings are conducted in workshop mode with more focus on hands-on sessions

View our other course offerings by visiting https://www.encartalabs.com/course-catalogue-all.php

Contact us for delivering this course as a public/open-house workshop/online training for a group of 10+ candidates.

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