The Intel Quartus Prime - Designing training course covers all the essential concepts and techniques required to design Intel FPGAs, including the use of the design, implementation, verification and debugging tools that are part of the Quartus Prime environment. This course is designed to meet the needs of all users, from those new to Intel Quartus Prime, to expert designers looking to maximise the potential of their Intel FPGA designs.
By attending Intel Quartus Prime - Designing workshop, delegates will learn:
- How to make best use of the full capability of the Quartus Prime software to implement your design.
- Reports and Clock Constraints, IO Constraints and Synchronous Interfaces, Source Synchronous Interfaces and Asynchronous Paths and Exceptions using TimeQuest.
- Use Incremental Compilation techniques, including creating LogicLock regions (Floorplanning) and Partitions to reduce compile times and more easily achieve timing closure.
- Estimating, analysing and optimising power consumption.
- Improve productivity and quality by automating the design flow using scripts.
- Functional and timing simulation using ModelSim.
- Debugging designs using SignalTap® Prime and SignalProbe.
- Advanced TimeQuest - Use of Tcl, Timing exceptions and Source-synchronous Interfaces.
- Timing Analysis for LVDS links
- Timing Closure, Incremental Compilation and Partial Reconfiguration
- Concept and use of LogicLock Regions for Floorplanning
- Knowledge of Digital and FPGA Design competence
- Knowledge of Verilog or VHDL languages is helpful
This Intel Quartus Prime - Designing class is recommended for:
- Existing users, who wish to become more productive by extending their knowledge of Quartus Prime and exploiting the latest features and techniques.
- Design engineers who are new to Quartus Prime, and want quickly to get fully up to speed with all the key features of Quartus Prime.