This Verilog training course teaches the application of the Hardware Description Language for FPGA and ASIC design. The syllabus covers the Verilog language, coding for register transfer level (RTL) synthesis, developing test fixtures, and using Verilog tools in the FPGA or ASIC design flows.
By attending Verilog workshop, delegates will learn:
- How Verilog fits into the FPGA or ASIC design flow
- How to use the Verilog language for hardware design and logic synthesis
- How to write thorough Verilog text fixtures to verify your designs
- How to avoid common mistakes when coding Verilog for synthesis
- How to use the specific Verilog tool flow you will be using on your project for simulation, synthesis, and where appropriate, FPGA P&R.
- Working knowledge of digital hardware design.
- Software Engineers